Network elements, such as switches and routers, are designed to forward network traffic, in the form of packets, at high line rates. One of the most important considerations for handling network traffic is packet throughput. To accomplish this, special-purpose processors known as network processors have been developed to efficiently process very large numbers of packets per second. In order to process a packet, the network processor (and/or network equipment employing the network processor) needs to extract data from the packet header indicating the destination of the packet, class of service, etc., store the payload data in memory, perform packet classification and queuing operations, determine the next hop for the packet, select an appropriate network port via which to forward the packet, etc. These operations are generally referred to as “packet processing” operations.
Modern network processors (also commonly referred to as network processor units (NPUs) perform packet processing using multiple multi-threaded processing elements (e.g., processing cores) (referred to as microengines or compute engines in network processors manufactured by Intel® Corporation, Santa Clara, Calif.), wherein each thread performs a specific task or set of tasks in a pipelined architecture. During packet processing, numerous accesses are performed to move data between various shared resources coupled to and/or provided by a network processor. For example, network processors commonly store packet metadata and the like in static random access memory (SRAM) stores, while storing packets (or packet payload data) in dynamic random access memory (DRAM)-based stores. In addition, a network processor may be coupled to cryptographic processors, hash units, general-purpose processors, and expansion buses, such as the PCI (peripheral component interconnect) and PCI Express bus.
Network processors are often configured to perform processing in a collaborative manner, such as via a pipeline processing scheme. For instance, some modern network line cards employ multiple network processors that are employed for performing a specific set of tasks, such as ingress and egress operations. In addition, some network processors, such as the Intel® IXP28xx series NPU, provide a single media and switch fabric (MSF) interface, which may be selectively configured to support either a System Packet Interface (SPI)-based interface or a Common Switch Interface (CSIX)-based interface in each of the transmit (Tx) and receive (Rx) directions. Under a conventional approach, multiple network processors of this type and/or other line card devices are connected via “fixed” interfaces, thus limiting the flexibility of the line card usage.
In further detail, FIG. 1 shows a line card architecture 100 including an input/output (I/O) block 102 including transceivers (XCVRs) 0-N coupled to a media interface (I/F) 104, NPUs 106, 108, 110, and 112, and a switching fabric interface 114. Each of NPUs 106, 108, 110, and 112 provide only a single media and switch fabric (MSF) interface having transmit and receive interfaces that may be configured a both media interfaces, switching fabric interfaces, or a mixed mode wherein one interface is used for media, while the other is used for the switch fabric. Under a conventional approach, the MSF interfaces are statically configured, and NPUs 106, 108, 110 and 112 are connected via fixed interfaces 116, 118, 120, 122, 124, and 126 in a daisy-chain configuration. This approach also requires some of the devices to function as pass-through devices, consuming a portion of the available bandwidth for those devices. For example, if NPU 106 desires to send traffic to the system's fabric via fabric interface 114, the traffic must first pass through NPU 118. This is inefficient. In addition, if one of the network devices fails, the entire daisy-chain is broken, resulting in a system with a single fail point.
Under the foregoing conventional approach, the line card is typically tailored to perform a particular set of applications. While this may apply to certain uses, it may not meet the functionality and/or throughput requirements of future uses. Accordingly, it would be advantageous to provide a flexible architecture that would enable the interfaces between various network line card devices to be reconfigured, thus providing a platform that can meet both present and future needs.